1. gate 2. source 3. drain absolute maximum ratings ta = 25 c note: *1 pulse width 10 s duty cycle 1% *2 measuring on ceramic board at 40 mm 38 mm 0.1 mm. absolute maximum rating pd without heat sink shall be made 150 mw. 1. gate 2. source 3. drain publication date: september 2012 ver. ced c storage temperature range tstg -55 to +150 mw channel temperature tch 150 c total power dissipation *2 pd 500 10 8 2.0 drain current drain current (pulsed) *1 code vgs gate-source voltage v id a idp a sot-323 20 v symbol drain-source voltage vds internal connection panasonic smini3-g1-b jeita sc-70 mtm13227 in smini3 type package y low drive voltage: 2.5 v drive y halogen-free / rohs compliant ? features y low drain-source on resistance:rds(on) typ. = 85 m ( vgs = 4.0 v) pin name MTM232270LBF silicon n-channel mosfet for switching unit: mm MTM232270LBF embossed type (thermo-compression sealing): 3 000 pcs / reel (standard) MTM232270LBF ? packaging 1 (eu rohs / ul-94 v-0 / msl:level 1 compliant) ? marking symbol: et parameter rating unit 2 3 1
? electrical characteristics ta = 25 c 3 c note: measuring methods are based on japanese industrial standard jis c 7030 measuring methods for transistors. *1 pulse test : pulse width 10 s duty cycle 1 % *2 see test circuit ver. ced ns turn-off time *2 toff vdd = 10 v, vgs = ? 4 to 0 v, id = 1 a 60 ns turn-on time *2 ton output capacitance coss input capacitance ciss id = 1 a, vds = 10 v, f = 1 khz 3.0 drain to source on-state resistance *1 rds(on)1 m rds(on)2 MTM232270LBF 2 1.3 id = 0.5 a, vgs = 2.5 v 100 150 s vds = 10 v, vgs = 0, f = 1 mhz 12 20 reverse transfer capacitance vdd = 10 v, vgs = 0 to 4 v, id = 1 a crss 26 10 a v 290 pf id = 1 a, vgs = 4 v 85 110 id = 1.0 ma, vds = 10 v 0.4 0.85 v 10 a 20 zero gate voltage drain current idss vds = 20 v, vgs = 0 v unit parameter min typ max symbol conditions vdss id = 1 ma, vgs = 0 v forward transfer admittance *1 |yfs| drain-source breakdown voltage vgs = 8 v, vds = 0 v gate-source threshold voltage vth gate-source leakage current igss
*2 test circuit ver. ced MTM232270LBF 3 vin 0 v 4 v pw = 10 s d.c. Q 1 % vin vdd = 10 v vou t id = 1 a rl = 10 d s g 50 90 % 10 % 10 % t (on) t (off) vou t vin 90 %
ver. ced capiacitance - vds MTM232270LBF dynamic input/output characteristics 4 id - vds id - vgs vds - vgs rds(on) - id ?`` 0 1 2 3 4 5 01234 total gate charge qg (nc) gate-source voltage vgs (v) vdd = 10 v 0 0.5 1 1.5 2 0 0.1 0.2 0.3 drain-source voltage vds (v) drain current id (a) vgs = 1.5 v 2.0 v 2.5 v 4.0 v 0 0.05 0.1 0.15 012 gate-source voltage vgs (v) drain current id (a) 25 ta = 85 -30 0 0.1 0.2 0.3 0.4 0.5 0123456 gate-source voltage vgs (v) drain-source voltage vds (v) id = 1.0 a 0.5 a 0.25 a 10 100 1000 0.1 1 drain current id (a) drain source on-state resistance rds(on) (m ) vgs = 4.0 v 2.5 v 1 10 100 1000 10000 0.1 1 10 100 drain-source voltage vds (v) capacitance c (pf) ciss coss crss
ver. ced MTM232270LBF safe operating area 5 vth - ta rds(on) - ta pd - ta rth -tsw 0.001 0.01 0.1 1 10 100 0.01 0.1 1 10 100 drain-source voltage vds (v) drain current id (a) idp = 8 a operation in this area is limited by rds(on) ta = 25 c, glass epoxy board (25.425.4t0.8mm) coated with copper foil, which has more than 300mm 2 . 100 ms 1 s dc 1 ms 10 ms 0 0.5 1 1.5 -50 0 50 100 150 temperature ta (c) gate-source threshold voltage vth (v) 0 50 100 150 200 -50 0 50 100 150 200 temperature ta (c) drain-source on-state resistance rds(on) (m ) 2.5 v vgs = 4.0 v 0 0.2 0.4 0.6 0.8 0 50 100 150 temperature ta (c) total power dissipation pd (w) mounted on ceramic board (40 x 38 x 0.1 mm) 10 100 1000 0.1 1 10 100 1000 pulse width tsw (s) thermal resistance rth ( c/w) non-heat sink
ver. ced 6 MTM232270LBF unit: mm smini3-g1-b ? land pattern (reference) (unit: mm)
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